培训方式以讲课和实验穿插进行
课程描述：
Course Objectives
1) Acquire basic skill to analyze and optimize for power using Synopsys Power Complier
2) Use prime Power to perform full—chip, accurate dynamic power analysis?
Course target
Design engineers who perform gate level power analysis?
Prerequisite?
You should have experience in the following areas:?
Understanding of digital IC design
Working knowledge of Design Complier
Knowledge of Verilog or VHDL Simulation
Experience with UNIX and text editor
Writing scripts using Tcl
Reading and lingking a gate—level netlist in PT or DC
Simulation of designs in Verilog or VHDL
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