The class begins with how to load the required synthesis and physical data required by IC Compiler (data setup), followed by creating a floorplan, including power grid, to meet timing and routeability throughout the flow (design planning). The placement flow focuses on optimizing the placement and logic for timing, congestion, power, and scan-chain ordering. The CTS unit covers controlling and building clock trees and performing additional timing optimization, followed by routing of the clock nets. In the routing unit, you will learn the signal routing and optimization steps based on the Zroute mode, including concurrent via doubling and antenna fixing. The chip finishing unit includes steps to improve yield and reliability, including wire spreading/widening, diode insertion, inserting filler cells, redundant via insertion, and metal filling.
Every lecture is accompanied by a comprehensive hands-on lab.
- Perform data setup, which includes loading required synthesis and physical data, creating a Milkyway design library, and applying common timing and optimization controls
- Create a non-hierarchical chip-level floorplan that will be routable and will achieve timing closure
- Perform placement and related optimizations to minimize timing violations, congestion, and power
- Analyze congestion maps and timing reports
- Perform pre-CTS power optimization
- Perform clock tree synthesis
- Analyze clock and timing results post-CTS
- Route the clock nets
- Execute a Zroute-based signal routing flow, with concurrent via doubling and antenna fixing
- Analyze and fix physical DRC and LVS violations
- Perform functional ECOs
- Perform chip finishing steps
- Generate output files required for final validation/verification